Thanks! That one I had not noticed
For the shifter on Spartan-6 one could use two dsp48a1 cores to make 18-bit barrel shifter, page 35
https://www.xilinx.com/support/documentation/user_guides/ug389.pdfHad a look at that 030-core, there's no way to fit that on xc6slx9 144-pin Spartan. Managed to fit it to xc6slx45 bga Spartan. It used 5,119 out of 6,822 slices (75%)
EDIT:
What I'd like to have is basic 68000 with some things taken from 68010, CPU32 and 68020.
From 68010 of course that loop thing + VBR.
From CPU32 a short pipeline.
From 68020 fetching 32-bit opcode when possible.
(4. If the instruction is a single-word instruction causing a branch, the second word is not used.
But because this word is fetched by the preceding instruction, it is impossible to avoid this
superfluous fetch.) Except when the second word is fetched at the same time as the word being executed when read through 32-bit bus then there is no time penalty.
Plus I would not mind if it ran with clock speeds above 100MHz or so.
Bus negotiating would also be mirrored, no one could ask the bus but my Spartan would ask for it... for Amiga use of course.
Also a Quad SPI eeprom housing kickstart, so a dual/triple bus. Quad SPI (with ICache), 16-bit parallel motherboard bus and or combined to 32-bit parallel bus.
That 030-core was wider than taller, I want massively parallel units, e.g the design should be taller than what it is wide.
EDIT:
What I also think I've learned is that reset signal as mostly used on VHDL codes is really not a reset at all. FPGA comes out of reset when it has loaded the configuration bitstream, if one truly wants to reset the FPGA then it needs to be reprogrammed. STARTUP_SPARTAN6 primitive should provide that from fabric logic. Signals etc. should have default state stated and they are programmed to that state at the same time as the logic is programmed.
EDIT: With a quick test this seems to work just nicely, also GTS sets pins to high impedance.
EDIT: In order to have any change to fit any 68000 core on to this Spartan-6 (xc6slx9 144-pin package) I need to target it specifically, e.g use what is already in silicon and not use for those things the logic fabric.
Why this part? It is easily soldered smd component, not a bga part.
CFGCLK Output 1 Configuration logic main clock output.
CFGMCLK Output 1 Configuration internal oscillator clock output.
CLK Input 1 User startup-clock input
EOS Output 1 Active high output signal indicates the End Of Configuration.
GSR Input 1 Global Set/Reset (GSR) input (GSR cannot be used for the port name).
GTS Input 1 Global Tristate (GTS) input (GTS cannot be used for the port name).
KEYCLEARB Input 1 Clear AES Decrypter Key input from Battery-Backed RAM (BBRAM).
STARTUP_SPARTAN6_inst : STARTUP_SPARTAN6
port map (
CFGCLK => open,
CFGMCLK => open,
EOS => open,
CLK => '0',
GSR => not nRESET,
GTS => not nRESET,
KEYCLEARB => '0'
);
EDIT: For the e-clock generating I plan on using the PLL_ADV primitive, when fed with 7MHz from the motherboard I can set a divider for it to produce 0.7MHz clock with correct duty cycle as that is also programmable. Synchronization would then be automatic as the 0.7MHz clock would be used to trigger and a signal set accordingly.
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VComponents.all;
entity pll_clocks is
Port ( CLK_50M : in STD_LOGIC;
RESET : in STD_LOGIC;
CLK_E : out STD_LOGIC;
CLK_7M : out STD_LOGIC;
CLK_200M_p1 : out STD_LOGIC;
CLK_200M_p2 : out STD_LOGIC;
LOCKED : out STD_LOGIC);
end pll_clocks;
architecture Behavioral of pll_clocks is
signal CLKFB : std_logic;
begin
-- Using MojoV3 we have 50MHz input clock
-- On Amiga we can get 3.54MHz 7.09MHz or multiples
-- PLL takes as low as 5MHz
-- Use PLL to generate e_clock
-- these are just some values used for testing, I have 100MHz scope with 20MHz sampling frequency... :)
-- 50MHz * 8 / DIVIDE
PLL_BASE_inst : PLL_ADV
generic map (
CLKFBOUT_MULT => 8,
CLKOUT0_DIVIDE => 50, CLKOUT0_PHASE => 0.0,
CLKOUT1_DIVIDE => 100, CLKOUT1_PHASE => 0.0,
CLKOUT2_DIVIDE => 100, CLKOUT2_PHASE => 90.0,
CLKOUT3_DIVIDE => 50, CLKOUT3_PHASE => 0.0, CLKOUT3_DUTY_CYCLE => 0.4,
CLK_FEEDBACK => "CLKFBOUT",
CLKIN1_PERIOD => 20.0,
DIVCLK_DIVIDE => 1
)
port map (
CLKFBOUT => CLKFB,
CLKOUT0 => CLK_7M,
CLKOUT1 => CLK_200M_p1,
CLKOUT2 => CLK_200M_p2,
CLKOUT3 => CLK_E,
CLKOUT4 => open,
CLKOUT5 => open,
LOCKED => LOCKED,
CLKFBIN => CLKFB,
CLKIN1 => CLK_50M,
CLKIN2 => '0',
CLKINSEL => '1',
DADDR => "00000",
DCLK => '0',
DEN => '0',
DI => "0000000000000000",
DWE => '0',
REL => '0',
RST => RESET --'0'
);
end Behavioral;
